This is a sample structural verilog file.

module fulladder ( carry, sum, in1, in2, in3 );
input in1, in2, in3;
output carry, sum;
wire   n3, n4;
xor U5 ( in1, n3, sum );
and U6 ( in3, in2, n3 );
aoi U7 ( in2, in1, n4, carry );
aoi U8 ( in1, in2, in3, n4 );
endmodule

This is my parser in python, using pyparsing.

from pyparsing import Group, delimitedList, Word, alphanums, Regex, cStyleComment, cppStyleComment, OneOrMore, Keyword, ParseException, Literal, ZeroOrMore, oneOf
import sys
def gate_inst_decl(s, loc, toks) :
print "Gate Declared"
print toks
def wire_decl(s, loc, toks) :
print "Wire Declared"
print toks
def input_decl(s, loc, toks) :
print "PI Declared"
print toks
def output_decl(s, loc, toks) :
print "PO Declared"
print toks
def inout_decl(s, loc, toks) :
print "PIO Declared"
print toks
def module_decl(s, loc, toks) :
print "Module ", toks[0][0], " declared"
def end_module(s, loc, toks) :
print "End Module"
if __name__ == '__main__' :
if not len(sys.argv) == 2 :
print "Usage : python %s <filename>.v" %(sys.argv[0])
sys.exit()
# The parsing grammar
identifier = Regex("[a-zA-Z_][a-zA-Z0-9_]+")
module_inst_name = Group(identifier).setParseAction(module_decl)
lparen = Literal("(").suppress()
rparen = Literal(")").suppress()
semi = Literal(";").suppress()
input = Keyword('input').suppress()
inout = Keyword('inout').suppress()
output = Keyword('output').suppress()
wire = Keyword('wire').suppress()
module = Keyword('module').suppress()
endmodule = Keyword('endmodule').suppress().setParseAction(end_module)
port_list = Group(lparen+ delimitedList(identifier) + rparen)
in_decl = Group(input + delimitedList(identifier) + semi).setParseAction(input_decl) | Group(input + identifier + semi).setParseAction(input_decl)
out_decl = Group(output + delimitedList(identifier) + semi).setParseAction(output_decl) | Group(output + identifier + semi).setParseAction(output_decl)
inout_decl = Group(inout + delimitedList(identifier) + semi).setParseAction(inout_decl) | Group(inout + identifier + semi).setParseAction(inout_decl)        wire_decl = Group(wire + delimitedList(identifier) + semi).setParseAction(wire_decl) | Group(wire + identifier + semi).setParseAction(wire_decl)
port_decls = in_decl | out_decl | inout_decl | wire_decl
gate_instances = Group(identifier + identifier + lparen + delimitedList(identifier) + rparen + semi).setParseAction(gate_inst_decl)
comment = cStyleComment.suppress() | cppStyleComment.suppress()
module = module + module_inst_name + port_list + semi + OneOrMore(port_decls) + OneOrMore(gate_instances) + endmodule
source = OneOrMore(module | comment)
# The actual parse
source.parseFile(sys.argv[1])